/////////////////////////////////////////////////////
// File Name: afifo_tb.v
// Author: zeping fan
// mail:   zpfan007@163.com
// Created Time: 2023年06月05日 星期一 20时34分00秒
/////////////////////////////////////////////////////

module afifo_tb();
    reg         rstn_i;
    reg         wr_clk_i;
    reg         wr_en_i;
    reg [7:0]   wr_data_i;
    reg         rd_clk_i;
    reg         rd_en_i;

    wire            wr_full_o;
    wire    [4:0]   wr_cnt_o;
    wire    [4:0]   rd_cnt_o;
    wire    [7:0]   rd_data_o;
    wire            rd_empty_o;

    always #5 wr_clk_i = ~wr_clk_i;
    always #20 rd_clk_i = ~rd_clk_i;

    initial begin
        $fsdbDumpfile("afifo.fsdb");
        $fsdbDumpvars(0,afifo_tb);
        rstn_i = 0;
        wr_clk_i = 0;
        wr_en_i = 0;
        wr_data_i = 8'b0;
        rd_clk_i = 0;
        rd_en_i = 0;
        repeat(2) @(posedge wr_clk_i);#0;
        rstn_i = 1'b1;
        repeat(2) @(posedge wr_clk_i);#0;
        wr_en_i = 1;
        for(integer i=0;i<8;i=i+1)begin
            wr_data_i = i;
            @(posedge wr_clk_i);#0;
        end
        wr_en_i = 0;
        repeat(4)@(posedge rd_clk_i);#0;
        rd_en_i = 1;
        repeat(6)@(posedge rd_clk_i);#0;
        rd_en_i = 0;
        repeat(5) @(posedge wr_clk_i);#0;      
        fork
            begin
                wr_en_i = 1;
                for(integer i=8;i<14;i=i+1)begin
                    wr_data_i = i;
                    @(posedge wr_clk_i);#0;
                 end
                 wr_en_i = 0;
            end
            begin 
                rd_en_i = 1;
                repeat(10)@(posedge rd_clk_i);#0;
                rd_en_i = 0;
            end
        join  
        wr_en_i = 1;
        for(integer i=14;i<17;i=i+1)begin
            wr_data_i = i;
        @(posedge wr_clk_i);#0;
        end
        wr_en_i = 0;
        #100;
        $finish;
    end



asyn_fifo#(
    .PTR_WIDTH(4),
    .DATA_WIDTH(8),
    .FIFO_DEPTH(2<<3)
)
u_afifo(
    .rstn_i(rstn_i),
    .wr_clk_i(wr_clk_i),
    .wr_en_i(wr_en_i),
    .wr_data_i(wr_data_i),
    .wr_full_o(wr_full_o),
    .wr_cnt_o(wr_cnt_o),
    .rd_clk_i(rd_clk_i),
    .rd_en_i(rd_en_i),
    .rd_data_o(rd_data_o),
    .rd_empty_o(rd_empty_o),
    .rd_cnt_o(rd_cnt_o)
);

endmodule
